The Binning IP core efficiently reduces the resolution of monochromatic images by combining adjacent pixels into a single output pixel. Ideal for applications that require lower data volume without compromising essential image content, it supports both summing and averaging binning methods. This IP core is optimized for high-performance image processing and analysis workflows..

• Runtime-configurable binning up to 32×32 pixels

• Supports image resolutions up to 4096×4096 pixels

• AXI-Stream data interface for high-speed data throughput

• APB interface for control and configuration

• Flexible binning modes: horizontal, vertical, and combined

• Two binning methods: summing and averaging

• Multi-pixel processing per clock cycle: 1, 2, 4, 8, 16, or 32 pixels

• Verified on Microchip PolarFire FPGA

• Demo project available for MPF300-VIDEO-KIT-NS

• Source RTL of the IP core

• Custom testbench for simulation

• Reference demo design