The 2DFIR IP core performs high-efficiency 2D convolution on monochrome images using user-defined kernels of up to 32×32 pixels. Designed for advanced image enhancement, feature extraction, and filtering, this core enables real-time processing of high-resolution images in hardware. It supports multiple operation modes, including configurable kernel switching and simultaneous multi-kernel filtering.

• Supports image resolutions up to 4096×4096 pixels

• User-defined convolution kernels up to 32×32 pixels

• Multiple operating modes:

  • Single Kernel Mode – standard convolution with one user-defined kernel

  • Configurable Kernel Mode – switch between predefined kernels at runtime

  • Multi-Kernel Mode – apply several different kernels to the same image in parallel

• AXI-Stream interface for data input/output

• APB interface for control and configuration

• Designed for low-latency, high-throughput image processing

• Verified on Microchip PolarFire FPGA

• Demo project available for MPF300-VIDEO-KIT-NS

The 2DFIR IP core performs high-efficiency 2D convolution on monochrome images using user-defined kernels of up to 32×32 pixels. Designed for advanced image enhancement, feature extraction, and filtering, this core enables real-time processing of high-resolution images in hardware. It supports multiple operation modes, including configurable kernel switching and simultaneous multi-kernel filtering.

• Source RTL of the IP core

• Custom testbench for simulation

• Reference demo design